How can I generate a three-input NAND gate with two-input NAND gates

Let's suppose I have this term here

NOT (ABC) (It's a NAND of ABC)

How can I get exactly the same thing with 2-input NAND GATES?

1. Generate A AND B from A NAND B by connecting a second 2-input NAND gate (with one input tied HIGH) on the output of the first. (You could connect both inputs together on the second NAND gate, but it's better to just tie 1 input to logic 1).
2. Connect the output from the second NAND gate to one of the inputs of a third 2-input NAND gate.
3. Connect logic variable C directly to the other input of the third 2-input NAND gate
4. The output of the third 2-input NAND gate is NOT(A.B.C) as required.